module tb_bus_addr_gen();
  
  reg enable, order, clk, rst_n, clear;
  wire [1:0] addr_bus;
  bus_addr_gen ADDR_GEN
  (
    .addr_bus ( addr_bus ),
    .enable   ( enable   ),
    .clear    ( clear    ),
    .order    ( order    ),
    .clk      ( clk      ),
    .rst_n    ( rst_n    )
  );
  
  initial
    begin
      clk = 0;
      rst_n = 0;
      enable = 0;
      order = 1;
      clear = 0;
      #50
      rst_n = 1;
      enable = 1;
      #50
      enable = 0;
      #20
      clear = 1;
      @(posedge clk)
      clear = 0;
      order = 0;
      enable = 1;
    end
  always #10
    clk = !clk;
endmodule
